Infineon TLE 6220 GP – Smart Quad Low-Side Switch

General Description The TLE 6220 GP is a versatile low-side power switch featuring four independent channels, built using Infineon’s Smart Power Technology (SPT). It includes a Serial Peripheral Interface (SPI) for control and diagnostics, alongside four open-drain DMOS output stages designed to switch loads connected to ground. Designed primarily for 12V and 24V automotive and industrial applications, it’s equipped with embedded protection features. This makes it particularly suitable for controlling loads in engine management and powertrain systems, such as injectors, solenoids, relays, and other resistive loads. The outputs can be controlled directly in parallel using dedicated input pins (useful for Pulse Width Modulation – PWM), or serially via the SPI.

Key Features of TLE 6220 GP

  • Four independent low-side switch channels.
  • Integrated protection against short circuits, overtemperature, and overvoltage.
  • 8-bit SPI for serial data input and detailed diagnostic feedback.
  • Direct parallel control capability for the four outputs, enabling PWM applications.
  • Ability to be cascaded (connected in series) with other similar quad switches.
  • Low power consumption when idle (typically 20µA in reset state).
  • Inputs compatible with standard microcontroller logic levels.
  • Provides Electrostatic Discharge (ESD) protection up to 2000V (Human Body Model).
  • Environmentally friendly (RoHS compliant) and AEC qualified for automotive use.

Key Specifications of TLE 6220 GP

  • Supply Voltage (Vs): Operates between 4.5V and 5.5V.
  • Output Voltage Capability (Drain-Source): Can withstand up to 45V continuously.
  • Output Clamping Voltage (Vds(AZ)): Typically clamps at 53V (minimum 45V, maximum 60V) to handle inductive load switch-off.
  • On-State Resistance (RDS(ON)): Typically 0.32 Ohms at 25°C (increases to about 0.7 Ohms at 150°C) when carrying 1A.
  • Output Current (ID): Can nominally handle 1A per channel when all four channels are ON simultaneously (at 25°C ambient, mounted on PCB). Individually, channels can handle up to the current limit (minimum 3A).
  • Output Leakage Current (ID(lkg)): Very low, maximum 10µA when the output is off (in reset state).
  • Turn-On/Turn-Off Time: Typically 5µs (maximum 10µs) for a 1A resistive load.
  • Operating Junction Temperature (Tj): -40°C to +150°C.
  • Storage Temperature (Tstg): -55°C to +150°C.

Protection Mechanisms Each of the four output stages is independently protected. An active zener clamp limits the voltage across the power transistor (typically to 53V) when switching off inductive loads like solenoids. The outputs also feature current limiting, which activates at a minimum of 3A (typically 4.5A, maximum 6A), to handle overload conditions or shorts to the power supply. If an overload or short circuit causes the current limit to activate, the device provides an early warning via the diagnostic interface (HL status code). If prolonged overload leads to overheating, a thermal shutdown function activates (typically around 170°C, maximum 200°C), putting the affected output into a low-duty-cycle pulsed mode to prevent damage. The output automatically restarts once the temperature drops by about 10°C. These protections are designed for fault conditions and should not be used as part of normal, continuous operation.

Control Methods The four output channels can be controlled in two main ways:

  • Parallel Control: Using the dedicated input pins (IN1, IN2, IN3, IN4). These inputs recognize a low voltage below 1.0V (VIL max) and a high voltage above 2.0V (VIH min), with a typical hysteresis of 100mV. The behavior (whether inputs are active-high or active-low) is set by the PRG pin (high = high-active, low = low-active). The state of each output is determined by a programmable logic operation (either OR or AND) between its parallel input signal and the corresponding data bit sent via SPI. If parallel inputs are left unconnected, internal pull-up/pull-down resistors (typically 50µA current) ensure the outputs remain off.
  • Serial Control (SPI): Using the standard SPI protocol (CS, SCLK, SI, SO pins). An 8-bit command is sent via the SI pin. This byte contains 4 control bits (to set modes like diagnosis-only, input read-back, SPI echo, OR logic, AND logic) and 4 data bits (to directly set the ON/OFF state of each channel). Data is latched on the rising edge of the CS signal. The OR logic operation is the default after reset or power-up.

SPI Interface Signals

  • CS (Chip Select): Active low. Enables communication. Input has an internal pull-up (typically 20µA). When high, SO is high-impedance, and SI/SCLK are ignored. Transitions trigger specific actions (latching data, loading diagnostics).
  • SCLK (Serial Clock): Clocks data in (on falling edge) and out (on rising edge). Maximum frequency is 5 MHz. Minimum high and low times are 50ns. Input has an internal pull-down (typically 20µA). Should be low during CS transitions.
  • SI (Serial Input): Receives serial data from the microcontroller (MSB first). Requires 20ns setup time before SCLK falling edge and 20ns hold time after. Input has an internal pull-down (typically 20µA).
  • SO (Serial Output): Sends diagnostic data back to the microcontroller (MSB first) when CS is low. Output voltage is close to Vs (Vs – 0.4V max) for high state (at 2mA) and near ground (0.4V max) for low state (at 2.5mA). Data is valid typically within 110ns (max 150ns depending on load) after SCLK rising edge. Goes high-impedance typically within 150ns after CS goes high.

Reset Functionality Driving the RESET pin low (minimum duration 10µs) clears the SPI registers, turns all outputs OFF, and puts the device into a very low power state (typically 20µA supply current). The pin has an internal pull-up resistor (typically 50µA current). Normal operation requires RESET to be high.

Diagnostics The TLE 6220 GP provides diagnostic information about the status of each output channel. A fault condition requires a minimum duration (fault delay time, typically 110µs, max 200µs) before being reported.

  • FAULT Pin: An open-drain output pin that signals a fault condition (like overload, short circuit, or open load) on any of the four channels by going low. It can sink at least 1.6mA while maintaining a low voltage (max 0.4V). This can be used to trigger an interrupt on the microcontroller.
  • SPI Diagnostics (SO Pin): Detailed status can be read serially. In ‘Full Diagnosis’ mode (using specific SPI commands like LLHH or HHHH), two bits per channel are returned via the SO pin, indicating:
    • HH: Normal function.
    • HL: Overload, Short Circuit to Battery (SCB), or Overtemperature (current limit active or thermal shutdown active).
    • LH: Open Load. Detected if the output drain voltage is below a threshold (typically Vs – 2V, range Vs-2.5V to Vs-1.3V) when the output should be ON. An internal pull-down current (typically 90µA) helps detect this.
    • LL: Short Circuit to Ground. Detected if current flows from the drain to ground (typically more than 100µA, range 50µA to 150µA) when the output should be OFF (and drain voltage is below Vs – 2.9V typically). Diagnostics are latched when CS goes low and reset when CS goes high. A short delay (up to the maximum fault delay time of 200µs) is recommended after changing output states before reading diagnostics to allow signals and detection logic to stabilize.
  • Other Diagnostic Modes: Specific SPI commands allow reading back the state of the parallel inputs (HHLL command, to check wiring) or enabling an SPI echo function (HLHL command, to test the serial communication link). The HHLL command also provides a simplified 1-bit fault status per channel (H=no fault, L=fault).

Environmental Information This product is available as a “Green Product,” indicating compliance with RoHS regulations (lead-free finish on leads, suitable for lead-free soldering).