Overview of Level 3 power FET PSpice simulation models
For SIMetrix and Cadence OrCAD Capture
Introduction
Level 3 PSpice models offer a realistic representation of IR HiRel’s power FETs through the integration of a thermal network and typical power FET electrical parameters within each model. These thermal networks offer engineers the opportunity to assess the dynamic behavior of a power FET’s junction temperature (Tj) and case temperature (Tcase) during real-time operation of power systems such as a buck converter. Several temperature-dependent electrical parameters such as drain-to-source on-resistance RDS(ON) are also designed to respond to fluctuations in Tj to better align the behavior of these power FET models with their physical counterparts.
PSpice model library files
These models for IR HiRel power transistors are intended to be evaluated with SIMetrix or Cadence OrCAD Capture PSpice simulators.
All IR HiRel Power transistor models are supported by benchtop measurement data and are constructed using PSpice simulation code. For SIMetrix, each IR HiRel Power transistor has a dedicated model library file (.lib) to support circuit simulation. A set of object library files (.olb) have been created to support Cadence OrCAD Capture.
Released Level 3 .lib and .olb files are available on the Infineon simulation model finder web page.
Integration of .lib files into SIMetrix
To design any circuit simulation that will incorporate IR HiRel power transistors, the necessary model library files must be installed into the simulator tool. This section details the necessary steps to install a PSpice .lib file into SIMetrix (using version 8.4, however these guidelines will be applicable for earlier software versions).
Integration of .olb files into Cadence OrCAD Capture
This section details the necessary steps to install a PSpice .olb file into Cadence OrCAD Capture (using version 22.1-2022, however these guidelines will be applicable for other software versions).
The following images detail a basic process to integrate a .olb file into the default library folder of a Cadence OrCAD Capture project.
Once integrated, the part exists as a library that can be found in the Part List of the project and can now be used in a schematic
Overview of Level 3 power FET PSpice models
Level 3 model pin description
Figure 8 shows the symbols that represent PSpice Level 3 models in SIMetrix for N-Channel and P-Channel power FETs, respectively. The additional two non-standard pins attached to the symbols are denoted as Tj and Tcase to represent the device’s junction temperature and case temperature respectively. Both temperature connections function as voltage pins where a measured voltage refers to temperature in a 1:1 conversion ratio (i.e. 25 V = 25°C). Typically, Tj is left open whereas Tcase cannot be left floating. To directly control a model’s Tj, set Tcase ≤ −301 V, and connect a voltage source to the Tj pin for it to operate at the desired Tj (see Figure 9).
Electro-thermal model description
To emulate dynamic self-heating and the subsequent shift in power FET electrical parameters, a Level 3 power FET contains a Cauer thermal network (generated from thermal impedance measurements of the part) coupled to the electrical model within the library file [2]. Dynamic self-heating is executed via Equation 1 where power dissipation is modeled as a current source that is fed into an appropriate Cauer network, (see Figure 10). The voltage measured at the Tj node represents the time-dependent junction temperature of the device that will subsequently influence temperature-sensitive electrical parameters
Implementation of an external heat sink
Figure 11 shows a heat sink (represented as a Cauer thermal network) connected to the model. The resistor components refer to Zth between the model case and the surrounding environment whereas the shunt capacitors represent thermal capacitance. The voltage source (V1) acts as the case temperature the device is subjected to.